Chinese Chipmakers Absorb Rising Costs to Bypass EUV Lithography Restrictions

Chinese semiconductor manufacturers are incurring higher costs and lower yields as they rely on deep ultraviolet lithography to produce advanced chips. Export controls have prevented the import of ASML’s extreme ultraviolet machines, forcing firms like SMIC and CXMT to use older equipment. This strategy involves exposing critical chip layers multiple times to achieve the necessary density, a process that increases the likelihood of defects and extends production timelines.

The reliance on DUV equipment stems from the limited availability of EUV tools, which use 13.5nm wavelength light to print fine features on processors. Analysts estimate the technological gap between China and Western nations is at least five years. Despite this constraint, SMIC demonstrated the viability of DUV-only production in 2023 when a teardown of Huawei’s Mate 60 Pro revealed its Kirin 9000S processor was manufactured using a 7nm-class process. Recent analysis suggests SMIC’s subsequent Kirin 9030 chip moved closer to 5nm density, though it still lags behind leading processes from TSMC and Samsung.

The technical method used is multiple patterning, where complex designs are split into simpler patterns and built up in stages. Chris Mack, co-founder of Fractilia, noted that industry standards previously suggested three exposures on a 193 immersion tool cost roughly the same as one EUV pass. However, at four masks, EUV becomes the more economical option. This shift means Chinese manufacturers are operating beyond the cost-efficient threshold for older tools.

Precision is a major challenge with this method. Each additional exposure introduces potential alignment errors and process variations. Designers often compensate by adding space around features, which enlarges the chip and reduces the number of usable dies per wafer. With wafers costing tens of thousands of dollars, this reduction in output is expensive. Mack emphasized that manufacturers sell finished dies, not raw wafers, making die yield a critical financial metric.

Memory chip production illustrates the efficiency disparity. Morgan Stanley estimated in June that CXMT produces approximately one-third as many bits per wafer as its Western competitors. The bank described lithography access as a hard ceiling for Chinese memory development. Mack added that process node labels have limited standalone meaning, noting that SMIC’s N+3 process, while an improvement, is less scaled than established 5nm processes from Samsung and TSMC.

DUV technology still has potential for further advancement. Micron developed its 1-alpha DRAM without EUV by using tight process control and multiple patterning. Morgan Stanley believes CXMT’s planned transition to 1-alpha DRAM for HBM3e is achievable without EUV. Douglas Fuller of Copenhagen Business School predicts that advanced packaging will allow DUV to support the latest DRAM generations by the end of the decade. Mack noted that China could make substantial progress if it leverages the full 193 immersion ecosystem, although he stressed that memory fabrication is easier than logic production.

EUV offers its own benefits, such as higher bit density. Micron’s 1-gamma DRAM, which uses EUV, delivers more than 30% greater bit density per wafer than its predecessor. However, EUV requires higher exposure doses to counter stochastic effects, adding to costs. Mack stated that he would find it difficult to believe 3nm or 2nm nodes would be economically viable without EUV support.

Chinese chipmakers are expected to continue expanding capacity while accepting larger dies and poorer yields. Morgan Stanley projects that CXMT will maintain its 1-alpha process without EUV but will increase its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new facilities. The bank also forecasts that China’s AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030, despite persistent gaps in EUV, high-bandwidth memory, and advanced software.